The Industry's Only Fully-Integrated PCI Express Solution
Providing a wide range of PCI Express analysis, emulation and compliance testing, Catalyst delivers the industry's only "Total Solution" for your PCI Express development requirements.
Analyzers | Exercisers | PCI Express Compliance Test Suites | COM-API, Programming Control | Real-time Protocol Error Detection | Performance Analysis | Performance Characterization | Advanced Triggering | PXP-100 Development Platform | Adapters, Extenders, and Accessories |Available Models: SPX-1A, SPX-1E, SPX-4A, SPX-4E, SPX-8E, SPX-8A
PCI Express Products
The Catalyst SPX Series of feature-rich PCI Express products are designed from the ground up to meet the specific requirements of engineering professionals developing PCI Express systems, devices, and software. Complete solutions are provided to support lane configurations from x1 to x16.
For x4 and below, Catalyst provides a fully integrated, single-board PCI Express analyzer/exerciser system, providing both passive in-line protocol analysis capabilities between two link devices, active endpoint or root complex emulation, protocol error detection, error injection, and automated compliance testing.
For designs at x8, the SPX Series offer two separate boards, one optimized for analysis and another optimized for exercising functions.
Back to topAnalyzers
In the analyzer mode, the SPX is inserted between two communicating PCI Express devices, typically a root complex and an endpoint. The analyzer provides extensive triggering and filtering, performance analysis, and an intuitive and detailed capture display of all layers of PCI Express traffic. Trigger scenarios may be set up for sequential or non-sequential events, including counter and timer functions. Selectable trigger events include all ordered sets, packets, K/D characters, protocol errors, payload data, and other bus events.
The captured data is displayed in an easy-to-understand Catalyst Trace™ view, with various display options available to quickly zero in on specific transactions, packets, errors, or other bus events. Alternatively, the user can elect to view the capture in a list view format, where bus traffic is represented in hex, 10b, binary, and name convention formats, by lane and direction.
One-touch filters are available to quickly strip away the physical, data link, and/or transaction layers. More sophisticated and detailed post-filter options are available as well.
A detailed statistical report provides instant qualitative and quantitative information on the captured bus traffic, including a fast-search feature whereby the capture instantly jumps to the selected packet or event highlighted in the statistics report.
A data payload report breaks down captured payloads and provides its own statistical summary on this information, including a byte value distribution graph as well as additional quick-search features. Additional features include save-as-text, copy options, quick filters, and various display control and formatting options.
The SPX is offered in two software feature packages, to better match user requirements with available budgets. The two configurations are the “Pro” SPX and the “Expert” SPX, with the Pro versions offering lower cost and the Expert versions offering a complete suite of advanced features. For details on these configurations, see here.
Analyzer Features and Controls
- Protocol error detection
- Multi-state event triggering
- Scramble/de-scramble options
- Precise pre- and post-filtering
- Non-standard link speed support
- Event counters
- Polarity reversal
- Spread Spectrum Clocking (SSC) Support
| FEATURES INCLUDED IN THE OPTION | Reduced "Pro" SPX | Full "Expert" SPX | ||
| Analyzer Features | Analyzer Projects | ![]() |
![]() |
|
| Easy Trigger/Capture Mode | ![]() |
![]() |
||
| Basic Trigger Patterns | Snapshot | ![]() |
![]() |
|
| Timer | ![]() |
![]() |
||
| Other Triggers: PERST#, WAKE#, Electric Idle, External Trigger In | ![]() |
![]() |
||
| Symbol | ![]() |
![]() |
||
| Ordered Set | ![]() |
![]() |
||
| TLP | ![]() |
![]() |
||
| Limited Protocol Errors (First 5) | ![]() |
![]() |
||
| Basic Capture Patterns | Exclude DLLPs | ![]() |
![]() |
|
| Exclude Ordered Sets | ![]() |
![]() |
||
| Exclude Idles | ![]() |
![]() |
||
| Symbol | ![]() |
![]() |
||
| Ordered Set | ![]() |
![]() |
||
| DLLP | ![]() |
![]() |
||
| TLP | ![]() |
![]() |
||
| Post-Processing | List View | ![]() |
![]() |
|
| Protocol Calc | ![]() |
![]() |
||
| Spec Header / Spec View | ![]() |
![]() |
||
| Auto Polarity Detection | ![]() |
![]() |
||
| Lane Reversal | ![]() |
![]() |
||
| Post Filter | ![]() |
![]() |
||
| Search | ![]() |
![]() |
||
| Advanced Analyzer Features | Advanced Analyzer Mode | ![]() |
||
| Sequential Mode | ![]() |
|||
| Advanced Trigger Features | Advanced Trigger Patterns | Timeout | ![]() |
|
| Message | ![]() |
|||
| Completion Status | ![]() |
|||
| Transfer | ![]() |
|||
| LTSSM | ![]() |
|||
| Unlimited Protocol Errors | ![]() |
|||
| Advanced Capture Features | Pre-Trigger / Post-Capture | ![]() |
||
| Advanced Capture Patterns | Message | ![]() |
||
| Completion Status | ![]() |
|||
| Trace Memory | 128 MB | 512 MB | ||
| Post-Process Reports | Statistical | ![]() |
||
| Data | ![]() |
|||
| Payload Decoding | Config Space Info | ![]() |
||
| Register Decodes | ![]() |
|||
| UDD | ![]() |
|||
| Compact View | ![]() |
|||
| LTSSM Flow Graph (1) | ![]() |
|||
| Auto Run | Auto Run | ![]() |
||
| Project Batch Run | ![]() |
|||
| Slow Speed | ![]() |
|||
| Cross Domain Trigger | ![]() |
|||
| Lane Width | x1 | ![]() |
![]() |
|
| x2 | ![]() |
![]() |
||
| x4 | ![]() |
![]() |
||
| x8 | ![]() |
![]() |
||
Notes:
(1) LTSSM Flow Graph Option requires Compact View Option enabled.
Back to top
Exercisers
In the exerciser mode, the SPX can become either a fully programmable endpoint or root complex, for purposes of testing and characterizing the corresponding link partner device. SPX series Exercisers have an embedded analyzer designed in to allow users to capture and trigger on the bus data while exercising.
The Catalyst Exerciser is a highly controllable, interactive PCI Express engine, allowing the ability to selectively turn on or off individual data link processes to test non-standard cases. Upstream and downstream modes are fully supported. Error injection capabilities also extend to the transaction and physical layers, where users can edit any TLP field with any value and can also inject lane skew on any/all lanes. A Record & Replay feature is implemented in the software as well as a Wait-For trigger to enhance the exerciser feature set.
The user can generate user-defined packets and primitives. All packet fields can be edited. Exerciser sequence controls include loop/iterate, pulse-out-on-execution, execute-on-external-pulse, and a Wait-For state, whereby execution is paused until a specific packet, event, or series of packet and/or events are detected on the bus.
Exerciser Features and Controls
- Inject lane skew
- Control Flow Control Updates and Initialization
- Control automated DLLP responses to Completions
- Force polarity reversal
- Replay captured packets
- Write/read/verify utility
- Data dump utility
- Read/modify/write utility
- Controllable replay buffer
- Controllable FC_INIT Values for multiple VCs
- WAIT-FOR conditional packet execution
- Non-Standard REF CLK support down to 40MHz
- Local read/write memory
PCI Express Compliance Test Suites, SpekChek
SpekChek is a unique, automated PCI Express compliance test suite that includes built-in emulation, verification and report generation. SpekChek, a software add-on to the SPX Series of Analyzer/Exercisers, is based on compliance checklists issued by the PCI Special Interest Group (SIG). SpekChek generates a predefined set up and stimulus to a link partner device, and then makes pass/fail decisions based on an expected response, automatically under software control. Once tests are complete, a formatted report is provided to the user, which lists all selected tests, and their pass/fail status. As each test is executed, a protocol capture file (trace view) is saved, as well as the project settings, which include exerciser and capture settings. These archives permit the user to view the exerciser's activities (or even edit them), and the actual response from the device under test to verify the pass/fail report. All files are provided in SPX Analyzer/Exerciser format and can be edited and viewed by this application software. Datasheet
Back to topCOM-API,Programming Control
A COM Application Programming Interface (API) is available, which permits the user to operate the SPX from a user-defined program, via the same Common Object Model (COM) library used by the Graphical User Interface (GUI). The COM API library exports interfaces to detect status, set options, and program the SPX hardware to perform various capture, trigger, exerciser, and performance operations. An easy mode is provided for simple tasks, and an advanced mode is provided for more detailed, complex tasks.
Back to topReal-time Protocol Error Detection
The SPX real-time protocol error feature allows the user to detect & trigger on over 40 protocol violations across all layers of the protocol, in real-time. The user simply selects the error, or errors, to be monitored and executes the run. Errors detected cause the SPX to trigger and display the error(s) at the trigger location in sync with the rest of the packets and events. Once the analyzer is armed with trigger on protocol error(s) it will continue to monitor the bus indefinitely until an error is detected or analyzer stopped by the user.
Back to topPerformance Analysis
The real-time performance analysis mode provides a graphical “finger-on-the-pulse” indication of bus activity. Metrics include bus utilization, throughput, completion latency, idle time, and other important characteristics. The performance analyzer may be run with or without the exerciser.
Back to topPerformance Characterization
The real-time performance analysis can also be operated in conjunction with the exerciser, allowing the user to characterize a design under precisely controlled conditions. For example, the exerciser may be used to loop through a script of read commands, while the performance analysis utility reports on average completion latency. Metrics include bus utilization, throughput, idle time, and other important characteristics.
Back to topAdvanced Triggering
The SPX application software provides two modes for control of the capture (filter) and trigger sequences. In the Easy Mode, an extensive list of pre-defined triggers and filters are provided for quick and simple execution of traffic captures. This mode is suitable for most common tasks. For more complex tasks, Catalyst provides an Advanced Mode interface, which gives the user a powerful, programmatic approach to controlling the capture/trigger process. This mode provides 24 sequencer states, including timers, counters, and IF, ELSE-IF, and GO-TO conditional logic. A graphical depiction of the sequencer logic is provided as well.
Back to top
PXP-100 Development Platform
Catalyst’s PXP-100 Development Platform provides an excellent out-of-system, self-contained, self-powered, portable test environment for PCI Express endpoint devices. The PXP-100 provides a passive backplane interconnect for all link widths, from x1 to x16. Two x16 slots are provided, with a standard mid-bus pad layout between the connectors for low-level electrical access by the Catalyst mid-bus probe solution or third-party logic analysis equipment. Power rails supplied include 3.3V, 3.3Vaux, and 12V, including power for the SPX Analyzer/Exerciser. A pushbutton for PERST# is also provided.
Back to topAdapters, Extenders, and Accessories
Catalyst provides a wealth of various active and passive adapters, extenders, and accessories for PCI Express technologies, including lane width adapters, a PIPE Speed Bridge, cabling accessories and adapters, ExpressCard and Mini-Express products. Click here for a complete listing of available adapters and extenders for these technologies.
Back To TopSPX-1A PCI Express Protocol Analyzer
Supports x1 lane configuration. Provides passive in-line analysis of PCI Express link traffic, including advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. May be field-upgraded or factory-configured to include PCI Express exerciser or additional lane support (to x4 configurations). See picture. Datasheet.
SPX-1A features include:
- Protocol analyzer
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 host control interface
- Protocol error detection
- Polarity & lane reversal
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- Optional COM API for programmatic control
SPX-1E PCI Express Exerciser with Integrated Data Capture Ability
Supports x1 lane configuration. PCI Express exerciser with standard, integrated analysis system (capture, trigger, and display). Configurable as endpoint or root complex. Includes advanced error injection capabilities at all layers, comprehensive packet generation features, advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. Compliance test suites and COM API optional. May be field-upgraded or factory-configured to include PCI Express Analyzer capabilities (see SPX-1A) or additional lane support (to x4 configurations). See picture. Datasheet.
SPX-1E features include:
- Protocol exerciser
- Integrated filter, trigger, & capture display
- Error injection
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 Host Interface
- SpekCheck compliance test (optional)
- Protocol error detection
- Record & playback
- Polarity reversal
- Configuration space decodes
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- COM API for programmatic control (Optional)
SPX-4A PCI Express Protocol Analyzer
Supports x4 and x1 lane configurations. Provides passive in-line analysis of PCI Express link traffic, including advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. May be field-upgraded or factory-configured to include PCI Express exerciser. See picture. Datasheet.
SPX-4A features include:
- Protocol analyzer
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 Host Interface
- Protocol error detection
- Polarity & lane reversal
- Configuration space decodes
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- COM API for programmatic control (Optional)
SPX-4E PCI Express Exerciser with Integrated Data Capture Ability
Supports x4 and x1 lane configurations. PCI Express exerciser with standard, integrated analysis system (capture, trigger, and display). Configurable as endpoint or root complex. Includes advanced error injection capabilities at all layers, comprehensive packet generation features, advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. Compliance test suites and COM API optional. May be field-upgraded or factory-configured to include PCI Express Analyzer capabilities (see SPX-4A). See picture. Datasheet.
SPX-4E features include:
- Protocol exerciser
- Integrated filter, trigger, & capture display
- Error injection
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 Host Interface
- SpekCheck compliance test (optional)
- Protocol error detection
- Record & playback
- Polarity reversal
- Configuration space decodes
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- COM API for programmatic control (Optional)
SPX-8E PCI Express Exerciser with Integrated Data Capture Ability
Supports x8, x4, and x1 lane configurations. PCI Express exerciser with standard, integrated analysis system (capture, trigger, and display). Configurable as endpoint or root complex. Includes advanced error injection capabilities at all layers, comprehensive packet generation features, advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. Compliance test suites and COM API optional. See picture. Datasheet.
SPX-8E features include:
- Protocol exerciser
- Integrated filter, trigger, & capture display
- Error injection
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 Host Interface
- SpekCheck compliance test (optional)
- Protocol error detection
- Record & playback
- Polarity reversal
- Configuration space decodes
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- COM API for programmatic control (Optional)
SPX-8A PCI Express Protocol Analyzer
Supports x8, x4, and x1 lane configurations. Provides passive in-line analysis of PCI Express link traffic, including advanced filter and trigger functions, intuitive packet capture display, list view display, link performance characterization tools, and various link control settings. See picture. Datasheet.
SPX-8A features include:
- Protocol analyzer
- Real-time performance analysis
- Statistical traffic analysis
- Ethernet & USB 2.0 Host Interface
- Protocol error detection
- Polarity & lane reversal
- Configuration space decodes
- Scramble/de-scramble options
- Non-standard link speed support
- Spread Spectrum Clocking (SSC)
- External triggers in/out
- COM API for programmatic control (Optional)







